Product Announcement: Synopsys Introduces PrimePower for System-on-Chip Design

Synopsys introduced an expanded power analysis solution called PrimePower aimed at accelerating system-on-chip (SoC) design closure. The tool extends signoff power analysis for earlier design implementation and accurate reliability analysis, the company says.

PrimePower provides power analysis reports for SoC designers to help them make timely optimizations to achieve power targets. Supported power types include peak, average, clock network, leakage, and multivoltage.

The tool builds a detailed power profile of the design based on the circuit connectivity, the switching activity, the net capacitance, and the cell-level power behavior data in the Synopsys database format library, according to the company. PrimePower also supports Nonlinear Power Model libraries.

“It calculates the power behavior for a circuit at the cell level and reports the power consumption at the chip, block, and cell levels,” Synopsys says. “When power analysis is complete, you can view design data and analysis results in the Graphical User Interface, including power maps and waveforms, for visual power debugging.”

Features:

  • Full-chip timing, SI and power analysis
  • Vector-free dynamic power analysis
  • Averaged power analysis
  • Time-based power analysis
  • Multi-voltage power analysis
  • Clock Network power analysis
  • PST-based power analysis
  • Cycle-accurate peak-power analysis
  • Cell electromigration analysis
  • Concurrent event analysis
  • Distributed peak power analysis
  • Concurrent multi-rail analysis
  • Close integration with PrimeTime Suite
  • Link with the RedHawk Analysis Fusion in IC Compiler II
  • Power ECO analysis

Chinese fabless semiconductor company HiSilicon builds AI-enabled SoCs that perform compute-intensive tasks throughout their service life.

“PrimePower enabled advanced reliability modeling and unique signoff-driven auto-fixing in our design flow, saving us weeks of design iterations while enabling lifetime robustness for these intelligent chips,” said Huatao Yu, senior manager of worldwide physical design at HiSilicon.

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